A frontside power-signal decoupling technology: self-aligned metal layer division and staggered patterning process

In this paper, we report a frontside power-signal decoupling technology based on self-aligned and staggered Metal-Layer Division (MLD) processing technique that effectively decouples the power rails from signal lines to achieve substantial metal capacitance reduction. The MLD metal configuration also significantly mitigates the interline capacitance and enhance the circuit performance in terms of both RC delay and power consumption. Our simulation results show that the MLD structure can help to reduce up to 31% BEOL capacitance compared with the conventional interconnect configuration. The key (septuple) patterning and metallization modules of this frontside decoupling technology are experimentally demonstrated using the PVD Ru sputtering and direct metal etch processes. It offers a cost-effective and possibly higher-yield alternative solution for addressing the critical challenges of hyper-scaled logic interconnects, thus delaying the need for a more complex backside power delivery system (BPDS) and high-NA EUV lithography.