Dry etch challenges for patterning middle-of-line (MOL) dual damascene contact trench and via in monolithic CFET (complementary FET)

The Complementary FET (CFET) architecture enhances transistor density by vertically stacking pMOS and nMOS transistors, offering a pathway for advanced scaling. However, this innovation introduces several process challenges, including the formation of reliable contacts to the source and drain of transistors. A critical area of research at IMEC, Belgium, focuses on optimizing contact routing through multilayer middle of line schemes to enhance intra-cell routing within reduced cell heights. This study presents the development and optimization of a Dual Damascene (DD) contact patterning process employing a trench-first via-last integration scheme for MOL integration in monolithic nanosheet-based CFET devices. Key topics include high aspect ratio (AR ~ 13 – 15) DD trench and via patterning sequences, advancements in plasma etch processes, and solutions to critical challenges. Particular emphasis is placed on optimizing hardmask thickness and improving via profiles and CD control to achieve self-aligned via structures. These findings support the advancement of nanosheet and CFET technologies, paving the way for next-generation semiconductor devices.