Wafer shape engineering for overlay improvement

The semiconductor industry is at a critical juncture where advanced node overlay budget is shrinking while process induced stressors are generating increasingly complex wafer distortions. With the advent of 3D architectures, this predicament has become exacerbated. A critical need exists to restore the wafer grid and alleviate traditionally non-correctable overlay error via shape engineering. A novel approach to mitigate wafer deformation via backside thin film patterning is proposed; resulting in greater than 20% reduction in overlay residual as compared to the baseline process.