Die-to-wafer advanced packaging: challenges for integration, yield, placement accuracy, and metrology

Die-to-Wafer (D2W) hybrid and fusion bonding is a very active area of development for both tool suppliers and end customers, with chiplet heterogenous integration transitioning from Low Volume Manufacturing (LVM) to mid and High-Volume Manufacturing (HVM), and baselines being established for High Bandwidth Memory (HBM) and CMOS Image Sensor (CIS) applications. However, D2W process flows present some considerable challenges within these various development cycles, especially with respect to tool and process integration, yield, placement accuracy, and metrology. A holistic approach for D2W HVM is being implemented which is comprised of cluster tool development supplemented by test vehicle design, placement accuracy improvement, and advanced metrology. Unique to this approach is a TEL Clean Carrier (TCC) that mitigates organic contamination associated with tape frame carriers, and in turn can enhance customer yield. The TCC approach also allows for leveraging of existing platform, plasma chamber, and wet processing chamber designs and technology without scaling these platforms and chambers to accommodate tape frames. In this paper an overview of the TCC, a comparison of bonding placement accuracy to lithography overlay accuracy, representative bonding data and in introduction to novel overlay metrology will be presented.