A Power Efficient Sleepy- Keeper and Lector Leakage Control Technique Based on SRAM Memory

Given the increasing demand for low power in IoT, mobile and embedded systems, leakage power consumption has become a major challenge in modern SRAM (Static Random Access Memory) designs. In this paper, we present a power efficient hybrid technique that combines the Sleepy-Keeper and LECTOR techniques to reduce static power dissipation in SRAM cells. The Sleepy-Keeper technique keeps the data integrity while reducing power consumption in idle states, while the LECTOR consumes power in a dynamic manner by cutting the CMOS structure with high resistance paths to decrease the leakage current. Finally, the proposed approach achieves large leakage reduction by combining these strategies. The proposed hybrid methodology is extensively simulated, and a comparative analysis is carried out between this hybrid methodology and conventional SRAM designs and standalone leakage control technology. Leakage power is reduced significantly, data retention in a standby mode is increased, and there is negligible impact on the read and write performance. It is a power efficient strategy that is highly suitable for energy constrained applications including portable devices, high speed cache memory and IoT based systems.