Implementation of FIR Filter Using Multiplexer Based Truncated Multiplier and Approximate Adders

The growing demand for high-performance digital signal processing (DSP) systems necessitates the development of efficient digital filters with reduced power consumption, area, and computational complexity. The two important components of digital filters are multiplier and adder. This paper presents the design and implementation of digital filters utilizing a multiplexer-based truncated multiplier. The proposed approach focuses on optimizing multiplication operations, which are a critical component in digital filters, by minimizing the hardware resource usage while maintaining acceptable accuracy for DSP applications. The design methodology is detailed, including the architecture of the multiplier, integration into finite impulse response (FIR) filter, and the overall system workflow. Simulation and synthesis results obtained from Xilinx and Spartan-3E FPGA board demonstrate the performance of the proposed filter in terms of area, power, speed, and accuracy. Approximate Adders are used in place of adders in the digital filters. The findings indicate that the proposed design achieves significant improvements in efficiency compared to conventional filter implementations, making it a viable solution for resource-constrained applications in areas such as audio processing, communications, and embedded systems.