Wideband Digital $N$ -Beam Delay-Sum Apertures at $\mathcal{O}(N)$ Complexity: Towards 64 GS/s 8-Beams on Intel Agilex-9 Direct-RF Chiplets

Formation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> simultaneous true-time delay-and- sum (DAS) RF beams from an N -element array of wideband antennas has many applications in wireless communications, electronic warfare, spectrum sensing, radar, and signals intel-Iiaence. A conventional DAS wideband beamformer scales as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N^{2})$</tex> different individual delay line segments (i.e., the delay complexity) which makes large arrays with many antennas and wideband beams impractical. This paper introduces a method based on the factorization of the approximate DFT matrix that reduces the delay complexity from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N^{2})$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N)$</tex> which in turn makes dense aperture antenna arrays with large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> elements lead to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> DAS beams at significantly smaller delay line count. Each delay can be realized in DSP as a FIR filter. Therefore, a wideband N -beam system at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N)$</tex> delay line complexity as opposed to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N^{2})$</tex> implies a significant reduction leading to smaller chip area and power consumption for hardware realization on a digital ASIC chip. We provide an overview of ongoing work on realizing an 8-beam DAS digital multi-beam beamformer using the state-of-the-art (SOTA) Agilex-9 Direct- RF chip lets from Intel which supports sample rates up to 64 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{GS}/\mathrm{s}$</tex> per channel.

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Published
2024-12-18
DOI
https://doi.org/10.1109/rfid-ta64374.2024.10965176
Primary Topic
VLSI and Analog Circuit Testing
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article

Wideband Digital $N$ -Beam Delay-Sum Apertures at $\mathcal{O}(N)$ Complexity: Towards 64 GS/s 8-Beams on Intel Agilex-9 Direct-RF Chiplets

Arjuna Madanayake, Sirani M. Perera
VLSI and Analog Circuit Testing
article

Wideband Digital $N$ -Beam Delay-Sum Apertures at $\mathcal{O}(N)$ Complexity: Towards 64 GS/s 8-Beams on Intel Agilex-9 Direct-RF Chiplets

Arjuna Madanayake, Sirani M. Perera
article en

Abstract

Formation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> simultaneous true-time delay-and- sum (DAS) RF beams from an N -element array of wideband antennas has many applications in wireless communications, electronic warfare, spectrum sensing, radar, and signals intel-Iiaence. A conventional DAS wideband beamformer scales as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N^{2})$</tex> different individual delay line segments (i.e., the delay complexity) which makes large arrays with many antennas and wideband beams impractical. This paper introduces a method based on the factorization of the approximate DFT matrix that reduces the delay complexity from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N^{2})$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N)$</tex> which in turn makes dense aperture antenna arrays with large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> elements lead to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> DAS beams at significantly smaller delay line count. Each delay can be realized in DSP as a FIR filter. Therefore, a wideband N -beam system at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N)$</tex> delay line complexity as opposed to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathcal{O}(N^{2})$</tex> implies a significant reduction leading to smaller chip area and power consumption for hardware realization on a digital ASIC chip. We provide an overview of ongoing work on realizing an 8-beam DAS digital multi-beam beamformer using the state-of-the-art (SOTA) Agilex-9 Direct- RF chip lets from Intel which supports sample rates up to 64 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{GS}/\mathrm{s}$</tex> per channel.

Florida International University (US), Embry–Riddle Aeronautical University (US)
Affordable and clean energy
Openalex Percentile: Top 67%
VLSI and Analog Circuit Testing
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