FPGA Implementation of an Efficient Hybrid Multiplier: A VLSI Architecture Utilizing Hybrid Adder Technology

The evolution of Digital Signal Processing (DSP) systems and embedded systems within the VLSI era has significantly impacted computational speed, chip size, and power consumption, consequently influencing the overall cost of systems. Multipliers hold a pivotal role in this context, as they are central to various DSP applications. These multipliers are often involved in computing additions for partial products and frequently perform logical operations. To improve the performance of these multiplier architectures, efforts have been made to reduce switching activity and area by employing combinational optimization techniques. This paper presents a novel approach by designing a hybrid multiplier architecture that combines different types of multipliers while leveraging optimization techniques. The hybrid multiplier architecture was designed and tested using the ISIM tool in Xilinx Vivado 2017.2. The experimental results clearly indicate that the proposed hybrid multiplier demonstrates improved speed and performance when compared to traditional multiplier designs, making it a valuable advancement in the field of digital signal processing and VLSI system design.