Performance Analysis of VLSI Architecture of Dadda Multiplier Using Divide and Conquer Strategy with Approximate Adders

Multiplication plays a pivotal role in diverse fields, including digital signal processing, scientific computing, machine learning, cryptography, computer graphics, control systems, finance, and embedded systems. Optimizing multiplication operations can significantly enhance performance and efficiency across these domains. This paper presents a VLSI architecture for a hardware multiplier module that utilizes the Dadda algorithm in conjunction with the Divide and Conquer strategy, incorporating Approximate Adders. These adders strike a balance between accuracy and resource efficiency, leading to reductions in power consumption and silicon area. Approximate Adders are essential in optimizing power, area, speed, and heat dissipation in digital systems, particularly in applications where absolute precision is not important. This work underscores the potential of integrating approximate computing with efficient multiplication techniques to advance digital circuit design. The architecture is implemented in Verilog, and its functionality is validated using Vivado 2023.2 and Cadence tools.