Performance Analysis of Wallace Multiplier Using Novel Approximate 4: 2 Compressors

Approximate computing is revolutionizing VLSI design by striking a balance between accuracy, power efficiency, and performance. This paper delves into the Approximate 4:2 Compressor, a vital component in arithmetic circuits like multipliers and adders, particularly in the context of Wallace multipliers(WMs), where it enhances speed and efficiency by reducing the complexity of partial product reduction. Utilizing tools such as Vivado 2023.2 ISIM and Cadence, we evaluate the compressor's performance across 180nm, 90nm, and 45nm technology nodes, revealing significant decrease in area, power consumption, and delay. Notably, the results show that approximate compressors achieve substantial hardware savings while maintaining acceptable accuracy. In error-tolerant applications such as image processing, signal processing, as well as machine learning, the benefits of these methods are especially notable, as minor inaccuracies can be tolerated. The capacity of these designs to adapt to various technology nodes showcases their flexibility in the dynamic VLSI landscape. Thus approximate compressors provide a revolutionary option compared to traditional designs, meeting the challenges faced in contemporary VLSI. This work emphasizes their potential to drive innovative, energy-efficient solutions in high-performance computing, showcasing the transformative impact of approximate computing on future technology.