Design and Evaluation of a Hybrid Adder Employing the Power Gating Method

The multiplexers (mux) select the final sum and carry, rendering the CSLA an inefficient area adder. Two rows of ripple carry adders are present. While the suggested AFPL logic can reduce power dissipation in the CBL based SQRT CSLA, the CBL based SQRT CSLA is preferred to address the problems of area efficiency and latency. The major objective is to use AFPL logic to develop a CBL-based SQRT CSLA-hybrid adder that will increase speed and reduce power dissipation.