Detrimental Voltage Elevation Phenomenon of the SGTOs and Its Optimization Methods

In this article, the mechanism regarding the detrimental voltage elevation phenomenon of the Super GTOs (SGTOs) is analyzed. Firstly, based on simulation, it is clarified that the ringleader of the voltage elevation is the insufficient carrier concentration. Secondly, the factors influencing the voltage elevation are studied through quantitatively theoretical analysis, and it is found that the voltage elevation can be reduced by improving injection efficiency, and decreasing the chip thickness. Thirdly, an optimization method to reduce the voltage elevation is proposed. Finally, sample SGTOs are fabricated and tested. The voltage fall time of the device is 70 ns. The di/dt of the device is 32 (kA/μs)/cm2 , indicating excellent pulse performance. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fig. 2. Voltage elevation under ultra-high di/dt conditions. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"/> <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fig. 2. Voltage elevation under ultra-high di/dt conditions. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"/>