Computational-aided etch process innovation
The device downscaling manifests the challenges of semiconductor manufacturing innovation. While there’re many, in a sense, the challenges come down to two major limitations: The phenomena are too fast or too small to measure, the tests are too expensive or too time-consuming to conduct, or both. The modeling and simulation play a suitable role to help address the issues. In the first part of talk, we introduce a variety of modeling approaches including atomistic chemical modeling, plasma and profile simulation. In addition to the capability, the limitations will also be discussed. In the second part of talk, we provide examples of combining modeling and experiment to investigate and improve the process. We will talk about the new chemistry screening, mechanism building, process tuning suggestion, and both plasma and non-plasma etch cases, etc. Through the paper, we intend to provide a high-level yet insightful view of the synergy of modeling and experiments on semiconductor manufacturing innovation. Hopefully, the sharing encourages the interdisciplinary discussions and collaboration.
Authors
- Yoshihide Kihara
- Akiteru Ko (ORCID: https://orcid.org/0009-0006-6699-4601)
- Du Zhang (ORCID: https://orcid.org/0000-0001-8921-5865)
- Yu-Hao Tsai
Institutions
- Tokyo Electron (Japan) (JP)
- In-Q-Tel (US)
Publication Details
- Published
- 2025-04-22
- DOI
- https://doi.org/10.1117/12.3051466
- Primary Topic
- Manufacturing Process and Optimization
- Type
- article
- Field-Weighted Citation Impact
- 0.00