Overlay distortion caused by backside defects: needs for improved track integrated backside cleaning towards high-NA EUV

Manufacturing a microchip involves more than a hundred process steps, each of which can lead to the contamination of the wafer backside. In the sequence of multiple process steps, contamination can accumulate on the wafer backside. Exposing wafers with the presence of backside defects can lead to various issues, such as damage to the scanner Wafer-Table (WT) and resulting in a reduction on its lifetime, increase in maintenance cost and decrease in productivity. Next to that, when clamping a wafer with defects at the backside in the exposure tool, a local deformation or clamping distortions of the wafer can appear. These distortions may result in focus loss or on-product overlay drifts, negatively impacting device performance. In previous work, we demonstrated that there is a clear correlation between backside contamination and focus loss which can lead to patterning failures for line/space patterns with a 40nm pitch exposed on a 0.33 Numerical Aperture (NA) EUV system. With further device scaling and the introduction of High NA EUV (0.55 NA), the impact of backside defects is expected to become even more significant, given the smaller depth of focus and overlay specifications required for 0.55 NA EUV systems compared to 0.33 NA. In this work, we focus on the second effect of backside contamination: clamping distortions that can lead to on-product overlay drifts. On imec EUV test wafers for CFET development, we identified a correlation between a focus spot detected by the NXE3400B scanner and the overlay performance on that location. Based on this observation, in collaboration with SCREEN, we set up a test vehicle where a first layer was exposed on an immersion system and etched into Si, followed by the patterning of a second layer on the ASML TWINSCAN NXE:3400B, aligned to the first layer. The overlay was measured on an ASML YieldStar 375 tool. This methodology allowed us to better understand the impact of backside defects on the overlay performance. Additionally, this method was used to evaluate new cleaning techniques on the SCREEN DT-3000 track-integrated backside cleaning module, as solution for removing critical defects on the wafer backside.