Wafer edge defectivity and its correlation to process parameters

Enhancing device yield is crucial for the adoption and economic viability of next-generation process technologies. Achieving high device yield near the wafer edge is particularly important and challenging because there are many more die near the wafer edge compared to the center, and maintaining process uniformity near the edge can be more difficult. For instance, plasma etch uniformity may differ near the wafer edge compared to the center, leading to tilted profiles or variations in critical dimension (CD) after etching. In lithography, maintaining overlay, leveling and focus control near the wafer edge can be more difficult than wafer center. With the advent of EUV lithography, focus offsets not only affect CD but also impact stochastic defectivity and pattern placement, thereby inducing numerous defects particularly around wafer edge. In this paper, we explore single layer defectivity on uniform EUV exposed wafers with a 28 nm minimum pitch logic metal pattern. We demonstrate how to distinguish defect contributions from etch and lithography processes.