Evaluating novel material stacks towards gate width roughness reduction

Gate patterning within the next generation transistor architectures have moved towards single expose EUV patterning. As the gate critical dimension and pitch scales down, there is an increasing focus on the reduction of EUV stochastics mediated effects on patterning. In particular, there is substantial interest in reduction of LER and LWR in the 40-50nm pitch regime to meet aggressive process assumption and device performance targets. Previously, we demonstrated low gate width roughness (GWR) through the introduction of a 3-beam conventional (monopole) illumination approach. The high NILS offered by this scheme was shown to be effective in reducing the low frequency gate width roughness. Here, we evaluate novel material stacks towards LER/LWR reduction at 40-50 nm pitches by combining the previously proposed monopole solution with next generation CAR and metal oxide resist platforms. Specifically, we evaluate the LCDU and LWR contributions to overall stochastics and evaluate roughness at device relevant length scales.