Advanced PnR logic patterning enabled by high-NA EUV lithography

This work presents the development of single-print metal logic patterning for A14 and A10 technology nodes using the TWINSCAN EXE:5000 at the ASML-imec High-NA lab, following successful pattern transfer via etch. The study focuses on random logic metal designs characterized by tight pitch constraints and aggressive tip-to-tip spacing, addressing the patterning challenges associated with advanced node scaling.

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Publication Details

Published
2025-04-22
DOI
https://doi.org/10.1117/12.3051054
Citations
1
Primary Topic
Advancements in Photolithography Techniques
Type
article
Field-Weighted Citation Impact
0.73
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article

Advanced PnR logic patterning enabled by high-NA EUV lithography

Atsushi Tsuboi, Arame Thiam, Bojun Cheng, Nobuyuki Fukui et al.
1 citations
Advancements in Photolithography Techniques
0.73
article

Advanced PnR logic patterning enabled by high-NA EUV lithography

Atsushi Tsuboi, Arame Thiam, Bojun Cheng, Nobuyuki Fukui, Chunzhi Gong, Víctor M. Blanco Carballo, Kaushik Sah, Yannick Feurprier, Joern-Holger Franke, Kathleen Nafus, Joost Bekaert, Werner Gillijns, Zhijin Chen, Yasser Sherazi, Balakumar Baskaran, Syamashree Roy, Hemant Vats, Ardavan Niroomand
article en
1 citations

Abstract

This work presents the development of single-print metal logic patterning for A14 and A10 technology nodes using the TWINSCAN EXE:5000 at the ASML-imec High-NA lab, following successful pattern transfer via etch. The study focuses on random logic metal designs characterized by tight pitch constraints and aggressive tip-to-tip spacing, addressing the patterning challenges associated with advanced node scaling.

Tokyo Electron (Japan) (JP), IMEC (BE)
Openalex Percentile: Top 29%
Advancements in Photolithography Techniques
0.73
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Advanced PnR logic patterning enabled by high-NA EUV lithography — Atsushi Tsuboi, Arame Thiam, et al. · (2025) | TGRS Research Map | TGRS