NA0.33 EUV extension for HVM: testing single patterning limits

The focus of this paper is to highlight IMEC's advancements in extending the resolution limit of 0.33NA EUV single patterning to 28 and to 26 nm pitch for advanced logic technology metal layers, as well as achieving a 32 nm contact-tocontact (C2C) pitch for logic vias, demonstrating progress in patterning technology to further push the boundaries of pitch scaling. We will show recent imec progress in achieving 28 metal pitch single patterning using NA 0.33 EUV on wafer. Separately, we will also show latest progress to pattern random via process down to 32 nm C2C. Our data will cover process window analysis (LER/LCDU, T2T variability and systematic and stochastic defects) looking for a workable Depth of Focus and a path to a lower the dose. Using the most advanced process technology, we will demonstrate the electrical performance of different proposed solutions (simple resistivity test or VC for vias). Different patterning options and their limits will be explored including the use of new underlayers(deposited/spin-on) for dose reduction up to 26%, new track-based development methods for defectivity reduction, complementary added directional etch based patterning to achieve T2T less than 15nm. Finally, through score cards, we will endorse low-NA extension readiness for the industry based on IMEC’s latest results.