Probing defects in metal oxide resists with an electrical yield vehicle

The industry is currently undergoing a transition from low-NA to high-NA EUV lithography. Metal Oxide Resists (MORs) will play an important role in extending the operating point of high-NA scanner to tight pitch. Understanding the impact that lithographic parameters of metal oxide resists have on the performance of high-NA relevant line/space pitches is mostly unknown. We have observed that the lithographic performance of a metal oxide resist differs significantly depending on the choice of underlayer, post-exposure-bake (PEB), and development technique. Developing an electrical defectivity vehicle that can assess both resist breaks and bridges and can be responsive to lithographic changes, overcomes the limitations of conventional e-beam or optical inspection-based defect metrology. In this presentation, we have assessed the impact that parameters such as underlayer, post-exposure-bake (PEB), and development optimization have on electrical yield for pitch 26 metal lines both for the current 0.33 NA EUV scanner, as well as the 0.55 NA EUV scanner.

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Published
2025-04-22
DOI
https://doi.org/10.1117/12.3054374
Citations
1
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
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article
Field-Weighted Citation Impact
0.73
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article

Probing defects in metal oxide resists with an electrical yield vehicle

Cyrus Tabery, E. P. De Poortere, Florian Gstrein, Víctor Blanco et al.
1 citations
Integrated Circuits and Semiconductor Failure Analysis
0.73
article

Probing defects in metal oxide resists with an electrical yield vehicle

Cyrus Tabery, E. P. De Poortere, Florian Gstrein, Víctor Blanco, Marie Krysak, Stéphane Larivière, Cheng‐You Yao, Bart De Wachter
article en
1 citations

Abstract

The industry is currently undergoing a transition from low-NA to high-NA EUV lithography. Metal Oxide Resists (MORs) will play an important role in extending the operating point of high-NA scanner to tight pitch. Understanding the impact that lithographic parameters of metal oxide resists have on the performance of high-NA relevant line/space pitches is mostly unknown. We have observed that the lithographic performance of a metal oxide resist differs significantly depending on the choice of underlayer, post-exposure-bake (PEB), and development technique. Developing an electrical defectivity vehicle that can assess both resist breaks and bridges and can be responsive to lithographic changes, overcomes the limitations of conventional e-beam or optical inspection-based defect metrology. In this presentation, we have assessed the impact that parameters such as underlayer, post-exposure-bake (PEB), and development optimization have on electrical yield for pitch 26 metal lines both for the current 0.33 NA EUV scanner, as well as the 0.55 NA EUV scanner.

Intel (United States) (US), ASML (United States) (US), IMEC (BE), ASM International (Belgium) (BE)
Openalex Percentile: Top 29%
Integrated Circuits and Semiconductor Failure Analysis
0.73
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