Moore’s law meets high-NA EUV: random via patterning for next-generation nodes

Constantly evolving with several revolutionary technologies, High NA EUV Lithography is at the forefront of the semiconductor industry. It enables the patterning of sub-10nm features, dramatically boosting transistor density and chip performance. This technology is essential for propelling Moore’s Law into the future. Early access to TWINSCAN EXE:5000 High NA EUV scanner, a state-of-the-art facility in the joint ASML-imec HNA EUV Lithography Lab, has enabled the exploration of leading-edge random via use cases. This access facilitates testing HNA EUV use cases, refining manufacturing processes, and accelerating innovation. In this paper, we share the result of imec’s first HNA EUV reticle. Key highlights of this work include demonstrating defect-free random vias with a 29.7nm center-to-center (C2C) distance, corresponding to underlayer metal grids of 22nm x 20nm pitch. We show excellent pattern fidelity showcasing LCDU~1.5nm, validating the process for even smaller via dimensions at 0.55 NA.