Stress evolution analysis of gate-all-around transistors: frontside and backside integration approaches

In this study, we present a comprehensive analysis of stress evolution in gate-all-around (GAA) transistors fabrication process by using advanced virtual fabrication techniques. We examined a frontside connect scheme and two backside connect schemes, including a direct backside connect (DBC) and a self-aligned backside connect (SABC) scheme. For each of these schemes, we studied the impact of S/D epitaxial SiGe on nanosheets only vs. epitaxial SiGe on both nanosheets and substrate. The results reveal that σxx, σzz, and the z-displacement are substantially altered for the backside connect scheme compared to the frontside connect scheme, providing a lever of control on carrier mobility. Notably, while σxx decreases between the epitaxial (EPI) growth and channel release steps, σzz increases. The z-displacement increases significantly during the backside Si recess step. Additionally, switching from an EPI on both nanosheet and substrate to EPI on nanosheet-only scheme does not alter the stress profile for the backside connect scheme. However, for the frontside connect scheme, this switch results in significant changes in the stress profile. Furthermore, we present the impact of the Ge fraction (x) in sacrificial Si1-xGex on the channel stress for these integration schemes. This work provides critical insights into stress distribution patterns and their dependency on the chosen integration methodology, offering valuable guidance for optimizing fabrication processes to enhance device performance.