Full field stitching-aware high-NA EUV OPC/RET flow

Upcoming generations of integrated circuits (e.g., below the 2nm device node) will be achieved with the help of anamorphic optics in high NA EUV scanners. Layers exposed on high-NA anamorphic scanners will require two or more stitched mask exposures to achieve the equivalent exposure area of previous-generation scanners. Stitched high-NA EUV patterned chips not only require stitch-friendly physical design awareness [1] but also require new extensions to the OPC and RET mask synthesis steps in order to ensure sufficient patterning control through process and mask variations. In this paper we review and show examples of different OPC and RET options to enable stitch-friendly patterning in high NA EUV. These results will include optimized sub-resolution assist feature (AF) placement for focus window enhancement, optimized sub-resolution grid (SRG) feature placement to reduce double exposure effects, mask-mask overlay sensitivity, dose/focus induced variation, the risk of AF printing during stitching and co-optimization requirements for stitching-friendly design decomposition.