Enhancing OPC accuracy in 28nm-class analog devices: addressing degradation in specific BEOL patterns through recipe tuning and simulation

In the fabrication of analog semiconductor devices, cost-effective process development is crucial. Unlike advanced digital devices, analog devices often rely on legacy fabrication methods, making the optimization of Optical Proximity Correction (OPC) particularly challenging. This study focuses on OPC enhancements for 28 nm Back-End-of-Line (BEOL) processes using a positive tone resist and single-mask lithography. Through wafer verification, several OPC-related failure modes were identified, including mask pattern fidelity degradation, asymmetric line/space (L/S) pitch instability, and bridging defects in Tip-to-Tip (T2T) line end patterns. Analysis revealed that discrepancies between OPC model predictions and wafer results were primarily caused by metrology errors, mask limitations, and insufficient pattern representation in the OPC dataset. To address these issues, three key improvements were introduced: (1) a mask fidelity-aware OPC retargeting strategy incorporating notch-filled and less aggressive corner serif adjustments, (2) a Pitch Walking method to mitigate pattern collapse in ABBA-type asymmetric L/S arrays, and (3) a specialized retargeting approach to improve T2T pattern robustness by reducing OPC model weight and refining Scanning Electron Microscope (SEM) measurement accuracy. Validation of the updated OPC flow demonstrated significant improvements in lithographic accuracy, as verified through wafer-level analysis. The application of these enhancements successfully reduced hotspot occurrences, improved pattern fidelity, and minimized lithographic defects. These findings highlight the importance of advanced OPC methodologies in cost-sensitive analog device manufacturing, offering a scalable approach to improving process stability and yield in next-generation semiconductor fabrication.