Optimization strategy and fabrication process of GAA hybrid-channel transistors: unique device performance booster and balancer

In this paper, we propose the concept of Gate-All-Around (GAA) hybrid-channel transistors such as Fin/Nanosheet-Nanowire MOSFETs and investigate their device behavior to address the electrical and yield limitations of standalone GAA nanosheet (NS) or nanowire (NW) device. TCAD simulation results including the DIBL (drain-induced barrier lowering) and SS (sub-threshold swing) characteristics reveal that gate control capability of a hybrid-channel nanosheet-nanowire (NSW) transistor is significantly enhanced to suppress the short-channel effect and reduce the leakage current, compared to an NS transistor. By optimizing the NW-to-NS width ratio, the NSW device’s gate control capability can be further improved, striking a balance between the performance gain (e.g., by continuously scaling down the gate length) and leakage reduction. Additionally, NSW transistor leverages the carrier mobility anisotropy on different crystal orientations to mitigate the performance imbalance between NMOS and PMOS. A refined self-aligned triple patterning (SATP) process is developed to fabricate ultra-narrow NWs with nanoscale gaps to adjacent NS channels, which offers a cost effective and production worthy patterning solution for NSW transistors to be competitive in future high-volume IC manufacturing.