EUV DRAM patterning historic overview and future assumption

The evolution of DRAM patterning has progressed from DUV to EUV lithography, enabling the scaling of sub10nm nodes in alignment with the Rayleigh equation parameters (λ, NA, K1). However, the scalability limitations of the 6F² DRAM cell architecture have slowed 10nm-class DRAM development, prompting exploration of alternative 4F² architectures and 3D DRAM integrations. EUV lithography has simplified processes by reducing mask counts, with high NA EUV emerging as a critical enabler for future nodes. Imec’s research highlights advancements in EUV patterning for critical DRAM layers like BLP/SNLP and capacitor holes, leveraging low-n masks, metallic resists, and computational simulations to optimize fidelity and process margins. High NA EUV shows promise for sub-30nm pitch patterning but faces challenges in depth of focus (DOF) and stitching effects. As AI-driven workloads increase demand for high-performance memory, 6F² DRAM remains vital, particularly in HBM applications. Future DRAM scaling will depend on innovations in EUV, High NA EUV, and hybrid patterning techniques, with 4F² and 3D DRAM architectures offering potential pathways for overcoming lithographic constraints. This paper reviews the past, present, and future of DRAM patterning, emphasizing the role of advanced lithography in enabling next-generation memory solutions.