An innovative stitching solution for multipatterning compliant routing metal layers beyond 2nm

Multipatterning technology is a class of technologies for IC manufacturing to make the density of features of a layer beyond the limitations of a single exposure lithography. As the semiconductor process further scales down to 2nm and beyond, the multi-patterning technology has emerged as the clear choice of the routing metal layers even within the era of extreme ultraviolet (EUV) lithography. The multi-patterning is a methodology analogous to m-coloring problem in graph theory, where polygons on the original layer are treated as nodes and the spaces between them, smaller than the minimum coloring distance, are regarded as links. The stitching technique within multi-patterning can divide a node into multiple nodes, each of which can be assigned to different colors to prevent color conflicts. This stitching approach is essential for resolving the m-coloring problem in real-world pattering process without increasing the number of masks or adding chip-area penalties. As chip manufacturing process continues to shrink, triple and quadruple patterning technologies (TPT/QPT) along with auto. stitching solution becomes more and more worthwhile for the chip scaling. But as the complexity of IC design escalates, identifying the optimal stitching locations for the congested routing metal layers becomes increasingly challenging. Synopsys IC Validator (ICV) provides a complete and integrated flow of TPT/QPT (Figure 1), featuring an innovative stitching methodology. The flow consists of three key steps. Step 1 (stitch candidates generation): Generating possible effective stitches after color conflicts are detected in the initial coloring. Step 2 (link mapping): Identifying spaces less than minimum coloring distance with these stitch candidates. Step 3 (recoloring with stitch candidates): Selecting and applying valid stitches among all stitch candidates to obtain TPT/QPT compliant layouts. This paper provides a concise explanation of the overall flow and how to generate and utilize the valid stitches that can guarantee TPT/QPT compliant layouts. Firstly, all potential stitch candidates that may resolve color conflicts will be generated, and our innovative solution determines the effective stitches by analyzing and counting the numbers of the links on each polygon. Secondly, detect spacing violations between new polygons formed by all stitch candidates to distinguish the stitch links, which are only created when specific stitches are placed, from all other links. Since the new node polygons after stitching overlap with each other (the overlapping parts are stitches), stitch links must be correctly transformed and recorded to reflect correct link-connection for final coloring. This process is known as link mapping, and one important reason for link mapping is that, if a stitch candidate is not selected in the end, the corresponding stitch links also should be removed for correct coloring in the later step. Finally, the process involves precise coloring, where the coloring engine selects the optimal stitches from the candidates based on the newly formed polygons and links. Through recursive removal of improper stitches and their associated links, the coloring engine tries to refine the layout to achieve the optimal coloring result. IC Validator’s stitching flow for TPT/QPT has demonstrated its effectiveness in managing the dense routing metal layers of the most advanced logic technology. By employing this sophisticated and integrated approach, we can achieve stringent chip-scaling targets while maintaining acceptable routing and coloring turnaround times. Finally, our proposed stitching solution can be seamlessly extended to more complex patterning technologies with a larger number of exposure masks (i.e. five, six masks, …), as needed. In summary, IC Validator’s stitching technology for the multi-patterning lithography is a valuable and efficient solution for auto. layout-fixing and ECO routing, ensuring high-quality results in the most advanced logic designs.