Mitigating stitching-induced performance and yield losses in high-NA EUV lithography: place and route implementation approaches

High-NA EUV (Extreme Ultraviolet) lithography with a 0.55 numerical aperture (NA) offers enhanced resolution for sub3nm technology nodes. However, its limited exposure field size necessitates multiple stitched exposure fields for large semiconductor designs, leading to stitching-induced variability and potential yield and chip performance loss. This paper presents a comprehensive approach using Place and Route (P&R) techniques to mitigate these challenges. The proposed methodologies include the application of region-specific design rules within stitching boundaries, optimized cell placement and I/O port positioning with stitching awareness, and stitch-aware cell layout optimization. Additionally, cost penalization techniques discourage routing layers from crossing stitch boundaries, and placement blockage controls are introduced to optimize signal routing. Experimental results demonstrate that these approaches mitigate design rule check (DRC) violations, routing congestion, core area overhead, and performance degradation caused by the stitch. The study compares four test cases: (1) a baseline design without stitch-aware methodologies, (2) optimized placement modules and I/O ports incorporating soft blockage, (3) routing allowance within the stitch region with relaxed design rules, and (4) stitch-tolerant standard cell design and placement. By applying these methodologies, DRC overhead due to stitching was reduced from 1,463 to 27, which in turn the area penalty from ~3% to <0.5%, and performance degradation was minimized from ~3% to ~0.2%. The results show that these methods progressively reduce DRC and performance degradation, with the final approach achieving near-complete compensation for High-NA EUV stitch-related losses. These findings highlight the importance of stitch-aware design strategies in ensuring optimal Performance-Power-Area (PPA).