Guided random synthetic layout generation and machine-learning based defect prediction for leading edge technology node development

The creation of a cutting-edge semiconductor technology node comes with many challenges in order to meet the performance and the manufacturing process yield requirements. Early in the process development phase, the manufacturing design rules are yet to be fully established. Hence, IC layout designers are partially engaged, and real designs are either very limited or non-existent. To overcome this hurdle, we apply synthetic layout generation to explore a yield-limited design space specifically for critical logic configuration at given technology definition. This leads to another challenge in the early development phase on how to efficiently identify process pinch points through inspection so that processes and design rules can be refined. In this paper we propose a flow to combine synthetic layout generation and machine-learning based defect prediction to accelerate new technology node development for logic devices. We start with limited ground rules for critical logic design, and create random guided synthetic layout. These patterns can complement existing functional and OPCV macros. Testchip SEM inspection on these patterns can identify multiple types of process hotspots in a concentrated region, improving the defect inspection efficiency. The silicon results can be used to calibrate a machine learning defect model. Hotspot analysis based on process and design related features can accelerate identification of the root cause. These hotspots can lead to refinement of litho, etch and CMP processes and/or update of a specific design rule, therefore, accelerating process node development and yield ramp. The process pinch points in functional design areas predicted through this method will be compared with traditional inspection methods.