Design enablement of low-cost stitching in high-NA EUV patterning

With introduction of the latest generation of High-NA EUV lithography machines with a higher Numerical Aperture (NA) of 0.55 (compared to the previous generation of 0.33NA EUV machines), ASML enables the semiconductor industry to print ever smaller features. However, the transition to High-NA EUV, also introduces anamorphic imaging, with a mask-to-wafer de-magnification that is different between the scan direction (8x) and the slit direction (4x). With a fixed mask size, this results in an exposure field that is half the standard size in the scan direction (16.5 mm instead of 33 mm), and full-size (26 mm) in the slit direction. To manufacture chips larger than the half-field exposure area, therefore two half-field exposures must be stitched together. One way to accomplish this is by imposing an exclusion zone at the stitch area between the two half-field 0.55NA masks to prevent shape-stitching issues for these layers. The higher-level, larger-pitch routing patterns can be made with full-field (0.33NA EUV and DUV) lithography, enabling connections across the lower-level half-field stitch zone, thus offering a simple and robust solution to the half-field stitching problem. In line with this approach, we propose overlay error tolerant stitch-aware design methodology for implementing the exclusion zone in the design while mitigating any potential yield losses. This study evaluates the performance and area, and design cost impact of implementing this methodology through a comprehensive Place-and-Route (P&R) implementation of both single-core and multi-core designs. For single-core designs, our analysis indicate a 2- 3% reduction in maximum frequency and a 1-3% increase in power dissipation. Additionally, our findings also reveal that the performance in single-core designs is highly dependent on factors such as exclusion zone width, the number of layers fabricated using High-NA EUV, and the exclusion zone’s placement location. For multicore designs, we explore various floorplanning strategies and introduce a stitch boundary placement optimizer designed to accommodate the exclusion zone while minimizing floorplan disruptions and macro redesign costs.