Analysis of Master Slave Interfacing of I2C Using Verilog HDL

Developed by Philips Semiconductor in the early 1980s, the Inter-Integrated Circuit (I2C) protocol is widely used communication standard that makes it easier for microcontrollers and peripheral devices to exchange data. This paper presents the design and implementation of I2C protocol using Verilog BDL. The two-wire bus topology (SDA and SCL) allows for bidirectional data transfer using both master and slave components in the proposed Verilog implementation. Key feature of this design is FSM design which provides little faster speed. The complete data transfer between the master and slave is observed through timing diagram in Xilinx Vivado tool version 2020.2. This paper also examines useful uses of I2C in consumer electronics, industrial automation, and embedded systems, emphasizing its adaptability and efficiency. The outcomes show how well the Verilog implementation worked to provide an adaptable and scalable I2C communication solution appropriate for contemporary electronic systems.