Power Electronic Implementation of Adjustable Finite Bandwidth Constant Power Loads

Power electronic loads are increasingly being adopted in various applications. Tightly regulated load converters act as constant power loads (CPLs) in a multi-converter cascaded system. The dynamics of a closed-loop controlled load converter make it behave as a finite bandwidth CPL. So, the availability of such a CPL is beneficial to evaluate the performance of a source converter in the laboratory. However, a provision for user-programmable bandwidth is typically unavailable in commercial CPLs. In this paper, a CPL with adjustable bandwidth is developed based on a synchronous buck converter (SBC). Closed-loop control implementation on an FPGA platform is explained using timing diagrams that are critical for its implementation. Practical considerations for number format selection for digital controller implementation are highlighted. Analytical estimations of settling times under step-change in power levels are validated using experimental measurements. The significance of an anti-windup scheme during closed-loop control implementation is shown experimentally.