A Novel Design of 3-bit Flash and 5-bit Sigma Delta Hybrid ADC sub - Range Architecture

Today with the advent of 5G networks, various high data rate applications like UHD video streaming, Remote Surgeries, Autonomous Vehicles, Smart Cities, Smart Buildings, Augmented Reality and Virtual Reality warrants newer designs of Gigabit Digital to Analog Converters and Analog to Digital Converters in 5G and 6G transceivers. In this paper, an 8-bit 3GS/s hybrid ADC for Low-power techniques are presented. It is designed as a sub-ranging architecture, with a flash 3-bit ADC in the first stage and a 4-channel timeinterleaved 5-bit Sigma Delta ADC in the second stage. The hybrid capacitive DAC modulates the segmented thermometer MSB capacitors and binary LSBs. The proposed architecture provides a very high sampling rate of 3 GSPS, good ENoB of 7.8 bit, low power consumption of 0.082 watts, SINAD of 49.6 dB, SNR 49 dB from 1.2v supply voltage.