Design and Development of a Low Power CMOS Based 18T SRAM Utilizing 45 nm Technology

There have been a lot of revolutions in the field of Static Random-Access Memories (SRAMs) by increasing the transistors, re-arranging the transistors etc. Generally, a basic SRAM has a pair of cross coupled inverters connected with several control transistors. In this paper more efficient innovation of 14T SRAM has been proposed having 18 transistors in design and it offers 76% of power reduction as per simulations. The simulations have been carried out in Cadence Virtuoso Tool and GPDK 045 has been used. The efficiency of 18T SRAM is achieved by adding 4 NMOS transistors which provides a faster scan decoupled path during operation. However, the results also show that the write speed is affected by adding NMOS which is making this device suitable for highly low power usage area only.