Low-Frequency Common Mode Voltage Mitigation in Si/SiC Based Ten-Switch Neutral-Point Clamped Converter

Power converter switching actions generate undesirable common-mode voltages (CMVs) and cause premature motor failure in drive applications due to voltage stress on the winding insulation system. The low-frequency CMV also brings challenges in CM inductive filter design for transformer-less solutions in grid integration of renewables. Through parasitic elements, CMV may also produce electromagnetic interference (EMI). This paper proposes methods for eliminating low-frequency CMV in a three-phase ten-switch neutral point clamped converter (TS-NPC). The converter is a low-cost alternative to existing three-level inverters such as NPCs and T-type converters, among others. However, the modulation methods available in the literature for TS-NPCI are not appropriate for reducing low-frequency CMV. The proposed modulation scheme of TS-NPC uses combinations of existing voltage vectors to generate a new set of zero CM voltage vectors (ZCVVs), The output voltage waveforms are produced using these ZCMVs following the voltsec balancing principle. The modulation also does not alter the inherent ability to balance the split capacitors' voltages of TS-NPC. An adequately designed switching sequence will allow for fewer switching events with no direct jump between the top and bottom DC links in the pole voltage waveform. Simulation results and comparisons with existing methods are provided to validate the proposed technique.