Control and Implementation Aspects of Totem-Pole Power Factor Correction Circuit in Digital Domain

A front-end power factor correction (PFC) circuit is usually employed in the ac to dc power conversion stage to maintain unity power factor. Digital signal processor (DSP) for controlling these circuits are becoming popular because of their advantages, such as flexibility, reproducibility, and fast development time. In digital implementation, delays such as sampling delay and modulation delay are present. In digital implementation, delays such as sampling and modulation delay are present. Sampling delay is caused by analog to digital (ADC) conversion, and modulation delay is caused by the uniformly sampled nature of the pulse width modulator. These delays can significantly impact the performance of the controller if not considered during the design stage. This paper designs the controller, including these digital delays. Also, the de-link voltage has a ripple with a frequency equal to twice the grid frequency, superimposed over the average de value due to a power mismatch between the ac and de sides. The controller should only respond to the average dc value, as fluctuations in the ripple voltage could impact the overall control performance. A digital filter eliminates this ripple voltage from entering the control loop. The totem-pole PFC circuit is fabricated to test the performance of the controller under various conditions, such as step change in de-link voltage reference and input voltage variations, such as voltage sag and swell.