Active Gate Driving Technique for the Voltage Balancing of Series Connected GaN Devices for Higher Voltage Application

GaN switches have better power density and lower switching/conduction loss than SiC switches. However, their acceptability is restricted due to their lower blocking voltage capability (maximum 650 V). Connecting two devices in series is the simplest solution to this problem. However, there is an issue of unequal voltage distribution even in well-matched switches, which leads to non-optimal utilization of the devices or, even worse, device failure. This voltage unbalance may either be due to gate pulse propagation delay or due to the presence of non-uniform parasitic capacitors across switches. This paper proposes an active gate driving method to balance voltages across two series-connected GaN switches with minimal voltage overshoot even in the presence of moderate loop inductances, parasitic gate capacitances, and gate pulse propagation delay. The simulation model for the proposed method has been developed and verified using LTspice incorporating commercially available GaN device GS66508T for a 900V DC link for two series-connected switches. To verify the technique's operability for other GaN devices too, a simulation was also conducted for two series connected EPC2304 for a DC link of 300 V. Voltage balance with minimal overshoot was obtained for both cases.