Design and Analysis of an Asymmetrical 21-Level Multilevel Inverter with Reduced Switch Count

This paper proposed an asymmetrical 21-level multi-level inverter comprising eight switches and three different rating voltage sources having a ratio of 1:2:7. The three voltage sources are used in different additive and subtractive manners to produce 21 output voltage levels. The level-shifted multi-carrier PWM technique generates gate pulses for the inverter. The theoretical analysis of the inverter is verified using MATLAB/Simulink software. The inverter is simulated under different load and modulation indices under steady-state and dynamic conditions. The inverter produces 5.68 % total harmonic distortion in the output voltage.