Voltage Multiplier Cell-Based Enhanced Quadratic Buck-Boost DC-DC Converter with Reduced Switch Current Stress

In this paper, a novel high gain quadratic DC-DC buck-boost converter which have extended boost region compared to its buck region counterpart is proposed. This topology is configured from a conventional topology by a novel arrangement of a switched inductor and a voltage multiplier cell. This novel arrangement helps to reduce voltage and current stress across switches and diodes compared to some of the conventional converters. This reduced stress enhances reliability of the devices. Furthermore, this topology facilitates continuous input current, non-inverted output voltage and self-voltage balancing across the switches. Steady state analysis and impact of parasitic elements on the efficiency of the converter are examined. The comparison between the proposed and similar conventional topologies is depicted in this paper. The experimental analysis has been conducted for a 200 W and 50 kHz hardware prototype of the converter with 48 V input voltage and 400 V output voltage, and the results are presented.