AIL-DNN: Modeling of IC Interconnect Parasitic Capacitances Based on Adaptive Incremental Learning

The accurate extraction of interconnect parasitic capacitance is a critical issue for designing VLSI circuits. To improve the efficiency of parasitic capacitance extraction, we present in this paper an adaptive incremental learning (AIL) strategy to build the parasitic capacitance extraction pattern model. The proposed model is a deep neural network (DNN) trained using adaptive incremental learning, or AIL-DNN. The key ideas are as follows: Firstly, the parametric space is divided into several subspaces called regions. And then a small number of training samples and test data are collected by Latin hypercube sampling (LHS); Secondly, a DNN model is trained and tested. The regions with large prediction errors are determined based on the average relative errors of test, which are called the training ineffective regions; Then, according to the ineffective regions, the sampling density is adjusted, that is, a new training dataset is prepared by adaptive resampling; Finally, incremental learning (IL) is used to make the DNN train new samples and update the network. The procedure of adaptive resampling, training and testing iterates until the test error reaches the predefined prediction accuracy. The proposed AIL-DNN can improve the efficiency and accuracy of DNN training with a reduced number of samples, and the trained DNN model can be used for the rapid extraction of parasitic capacitance. In this work, the prediction results of AIL-DNN and of the traditional DNN for two given interconnect patterns are compared. The results show that the size of training dataset required by AIL-DNN is about 20% of that of the traditional DNN with the similar accuracy. This significantly reduces the computational cost and time of dataset preparation.