Low-power V<sub>AQ</sub>-based one-side switching scheme for SAR ADCs

A VAQ-based DAC switching scheme is proposed to improve the power efficiency of SAR ADCs. The input signals are sampled onto bottom-plates of the most significant bit (MSB) capacitors, thereby eliminating the reset energy. The reference voltage VCM rather than VREF is switched during the third-bit cycle, thus significantly reducing the power consumption. Additionally, an energy-efficient one-sided switching technique is employed from the fourth-bit cycle. This proposed switching scheme achieves a 99.51% reduction in switching energy over the classic scheme. The ADC with the proposed switching scheme is designed in 0.18-μm CMOS technology. It consumes 37.7 nW at a sampling rate of 20 KS/s and 0.6 V supply, and achieves the ENOB of 9.59 bits, resulting in a figure of merit (FOM) of 2.45 fJ/conversion-step.