Comparative Analysis of Ternary Half Adder Using CNTFET

Ternary logic, a form of multi-valued logic (MVL), presents a promising alternative to traditional binary logic by enhancing computation efficiency, circuit density, and power savings. This study conducts a comparative analysis of two ternary half adder (THA) designs: a multiplexer-based approach and a decoder-based approach, implemented using carbon nanotube field-effect transistors (CNTFETs). The multiplexer-based THA utilizes 90 transistors, while the decoder-based design employs 74 transistors. Both designs were simulated using HSPICE with Stanford’s 32nm CNTFET technology at a supply voltage of 0.9V. The results highlight the trade-offs between transistor count, power consumption, and operational speed, providing insights into the efficiency and suitability of each design for low-power, high-performance ternary arithmetic circuits. The comparative evaluation underscores the advantages and limitations of multiplexer and decoder-based architectures in the context of nanoscale computing platforms.