Process‐Dependent Performance of Recessed‐Gate Enhancement‐Mode GaN p‐FET

There is a strong demand for GaN complementary logic (CL) circuits and power integrated circuits (PICs). The E‐mode p‐GaN gate high electron mobility transistor (HEMT) platform is a promising solution for GaN CL circuits. Compared to the commercialized E‐mode GaN n‐FET (i.e., the p‐GaN gate HEMT), the E‐mode GaN p‐FET has fallen far behind. To achieve E‐mode operation, gate recess is a common approach, but the channel thickness ( t ch ) and the surface roughness ( R q ) of etched p‐GaN significantly influence the performance of devices. This work investigates GaN p‐FETs with different gate recess depths. A pre‐treatment of the etched p‐GaN surface is used to smooth the etched p‐GaN surface. During the fabrication, t ch is found to be a critical process parameter that influences the performance of devices. As the t ch decreases, a more robust E‐mode operation (i.e., a more negative V th ) is achieved. However, this leads to an increase in on‐resistance ( R on ). When t ch = 8.5 nm, the fabricated E‐mode GaN p‐FET exhibits a V th of −1.1 V and a high I D‐max of 5.1 mA mm −1 . Compared to the E‐modep‐FET without pre‐treatment, the current density more than doubles. This work advances the development of p‐FETs on the standard E‐mode p‐GaN gate HEMT platform.