Design of Delay and Power Efficient Multiplier using AMM with Dadda’s Algorithm

Multiplication is a fundamental operation in digital signal processing, cryptography, and various computational applications.The efficiency of a multiplier is determined by key performance metrics such as area (LUT count), delay, and power consumption.This study presents a comparative analysis of three 8-bit multiplication architectures: Wallace Tree Multiplier, Dadda Multiplier, and a modified Additive Multiplication Module (AMM) integrated with Dadda's reduction algorithm.Each design is implemented and evaluated using Xilinx Vivado to assess hardware complexity, computational speed, and power efficiency.While Wallace Tree and Dadda multipliers utilize carry-save addition for partial product reduction, the modified AMM leverages Dadda's efficient reduction scheme to enhance performance.Experimental results show that the proposed AMM with Dadda's algorithm achieves improvements in power dissipation and delay compared to conventional designs.However, the LUT count is higher, indicating a trade-off between area and performance.These insights contribute to selecting an optimal multiplier for power-efficient and high-speed computing applications.