A Cost and Speed Co-Optimized Parallel Stochastic Multiplier for Binary Inputs Supporting Variable Bit-Widths

Stochastic circuits offer the benefits of small area and lower power consumption. However, as the bit width of the operands increases, the area and latency of stochastic circuits also need to increase exponentially to meet the precision requirements, resulting in a decrease in performance. This brief introduces a low-cost and high-speed parallel approximate stochastic computing multiplier (PASCM), which takes binary streams as both inputs and outputs. The PASCM is suitable for multiplication operations with multi-bit width. In order to further enhance the accuracy of the PASCM, an error compensation mechanism has been proposed. To verify the performance of PASCM, validation was conducted on FPGA. The experimental results indicate that the proposed design exhibits significant area and latency advantages among existing multipliers. Take 8-bit as an example, the PASCM shows a 48.33%, 18.61%, 45.74%, and 57.95% reduction in Look-Up Table (LUT), latency, power delay product (PDP), and area delay product (ADP), respectively, compared to the 8-bit precise binary multiplier implemented using an IP core. To further validate the design, the PASCM was constructed into Multiply-Accumulate units (MAC) and applied to several image processing algorithms on FPGA. The proposed multiplier showed excellent results in terms of peak signal-to-noise ratio (PSNR) and mean structural similarity index (MSSIM), with some algorithms achieving complete consistency with binary computation results, and the hardware performance also surpasses the most advanced designs.