Low-Latency and Area-Efficient Elliptic Curve Point Multiplication Architectures Over Koblitz Curves

Point multiplication is the core operation in elliptic curve cryptography. Koblitz curves are a special class of curves that can utilize the Frobenius mapping to accelerate the implementation of point multiplication operations. For point multiplication on Koblitz curves, this paper first proposes an optimized tNAF scalar conversion algorithm along with its corresponding hardware architecture. Additionally, for the computation of point multiplication, this paper proposes two optimal computational architectures: an area-efficient architecture and a low-latency architecture, both of which achieve the highest pipeline efficiency. The area-efficient architecture adopts a compact four-stage pipeline with a single multiplier, ensuring high circuit area utilization efficiency while achieving relatively low computation latency. The low-latency architecture implements two-stage and three-stage pipeline designs respectively in different binary fields, using two multipliers to reduce the clock cycles for point addition and further decrease the computation latency. The proposed architectures were implemented on Virtex-7 FPGA. For the GF(2163), GF(2283), and GF(2571) fields, the latency for the area-efficient architecture are 1.683μs, 3.455μs and 7.511μs, with slices usage of 3631, 7867 and 20612, and the point multiplication latency for the low-latency architecture are 1.347μs, 3.279μs and 7.071μs, with slices usage of 6026, 14246 and 38515. A comparison with state-of-the-art designs shows that the proposed point multiplication architectures offer significant advantages in terms of performance. In the GF(2163) field, the computation latency of the area-efficient architecture and the low-latency architecture is reduced by at least 21.158% and 43.952%, respectively. And in the GF(2283) field, the reduction in latency is 38.985% and 42.459%, while in the GF(2571) field, the reduction in latency is 58.111% and 59.720%.

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Publication Details

Journal
IEEE Internet of Things Journal
Published
2025-04-18
DOI
https://doi.org/10.1109/jiot.2025.3562194
Citations
1
Primary Topic
Cryptography and Residue Arithmetic
Type
article
Field-Weighted Citation Impact
3.25

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article

Low-Latency and Area-Efficient Elliptic Curve Point Multiplication Architectures Over Koblitz Curves

Yujie Jiang, Jingqi Zhang, Zhiming Chen, Jiawei Wang et al.
1 citations
IEEE Internet of Things Journal
Cryptography and Residue Arithmetic
3.25
article

Low-Latency and Area-Efficient Elliptic Curve Point Multiplication Architectures Over Koblitz Curves

Yujie Jiang, Jingqi Zhang, Zhiming Chen, Jiawei Wang, An Wang, Liehuang Zhu, Yue Hao
article en
1 citations

Abstract

Point multiplication is the core operation in elliptic curve cryptography. Koblitz curves are a special class of curves that can utilize the Frobenius mapping to accelerate the implementation of point multiplication operations. For point multiplication on Koblitz curves, this paper first proposes an optimized tNAF scalar conversion algorithm along with its corresponding hardware architecture. Additionally, for the computation of point multiplication, this paper proposes two optimal computational architectures: an area-efficient architecture and a low-latency architecture, both of which achieve the highest pipeline efficiency. The area-efficient architecture adopts a compact four-stage pipeline with a single multiplier, ensuring high circuit area utilization efficiency while achieving relatively low computation latency. The low-latency architecture implements two-stage and three-stage pipeline designs respectively in different binary fields, using two multipliers to reduce the clock cycles for point addition and further decrease the computation latency. The proposed architectures were implemented on Virtex-7 FPGA. For the GF(2163), GF(2283), and GF(2571) fields, the latency for the area-efficient architecture are 1.683μs, 3.455μs and 7.511μs, with slices usage of 3631, 7867 and 20612, and the point multiplication latency for the low-latency architecture are 1.347μs, 3.279μs and 7.071μs, with slices usage of 6026, 14246 and 38515. A comparison with state-of-the-art designs shows that the proposed point multiplication architectures offer significant advantages in terms of performance. In the GF(2163) field, the computation latency of the area-efficient architecture and the low-latency architecture is reduced by at least 21.158% and 43.952%, respectively. And in the GF(2283) field, the reduction in latency is 38.985% and 42.459%, while in the GF(2571) field, the reduction in latency is 58.111% and 59.720%.

IEEE Internet of Things JournalVol. 12(14)
Beijing Institute of Technology (CN), Peking University (CN), Beijing Microelectronics Technology Institute (CN)
National Natural Science Foundation of China, National Key Research and Development Program of China
Openalex Percentile: Top 10%
Cryptography and Residue Arithmetic
3.25
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