A subsampling PLL with dead zone controller for fast-locking

In this article, a subsampling PLL with a multi-dead zone controller is proposed. A dead zone controller is designed to automatically adjust the dead zone range based on the timing error, thereby switching the loop operating states to reduce the locking time while maintaining low in-band phase noise of the subsampling loop. The proposed SSPLL is fabricated in 55-nm CMOS technology. Simulation demonstrates the locking time is 2.3 μs, and when 150 mV and 300 mV voltages are applied, the re-locking times are 2.3 μs and 1.8 μs, respectively