A VLSI Architecture for MQ Arithmetic Encoder Supporting Three-Context Parallel Processing

JPEG2000 is a popular still image compression standard, which has excellent compression performance in the field of still image compression. At present, it is widely believed that MQ arithmetic encoder has become the most critical speed bottleneck of JPEG2000 algorithm due to the restriction of the serial execution mode of the algorithm itself. The MQ encoding is serial in nature, which is due to the high dependence between adjacent Cx-D pairs which severely affects its processing speed. In order to solve this problem, this paper proposes a multi-context MQ coding hardware architecture based on a partially parallel coding strategy. This architecture can process up to three Cx-D pairs in one clock cycle, which greatly improves the processing speed of the MQ arithmetic encoder under the existing architecture. In terms of overall performance, the encoder designed in this paper can process 2.64 Cx-D pairs per cycle on average, and 743.16 Cx-D pairs per second under TSMC90nm technology. The architecture is only 208399.66 units in area while achieving high throughput. The proposed MQ encoder provides a useful reference for hardware implementation of high performance algorithmic encoders in JPEG2000 and other image compression standards. At the same time, we comprehensively analyze the possible output scenarios of multi-bytecode streams caused by multi-context processing, and propose a processing structure based on additional pipeline, which greatly reduces the number of module fan-out and FIFOs.