Large Language Models for Printed Circuit Board Test Generation

We have made a study to explore the use of Large Language Models (LLMs) to automate test generation for printed circuit boards (PCBs). The evaluation of four LLMs and three prompting approaches on three PCB designs shows that LLMs can generate sufficient and accurate test steps when complexity and required number of test steps are low. However, with increasing design complexity, the accuracy decreases drastically. Of particular interest is that LLMs generated unspecified test steps, showing that LLMs can generate missing test steps and provide additional test coverage where the system designer might have missed. With further development and advancements of LLMs, it is likely that LLMs can achieve higher accuracy even for the more complex and advanced PCB designs, possibly automate the labor-intensive process of test generation, which will substantially reduce the time and cost associated with hardware testing.