Design and Analysis of a Boost Type Nine-Level Inverter with Reduced Switch and Capacitor Voltage Stress

This article proposes a boost type (BT) nine-level (9L) switched capacitor (SC) based transformerless inverter topology fo grid connected solar photovoltaic systems. It uses a single source, 10 switches, 2 diodes and 3 SCs. The voltage across the Sc is even which is only half of the output voltage v<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</inf>/2 and does not employ any complex algorithms for their voltage balancing. Power switches voltage stress is significantly low for the proposed topology and hence low total standing voltage per unit (TSV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p.u.</inf>). The different modes of operation and design of SC are presented. The simulation verification and prototype results are presented to confirm the operability of the proposed topology. Further, a detailed comparison of same art of topologies has been presented to highlight the features of the proposed topology.

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Published
2025-01-09
DOI
https://doi.org/10.1109/icaect63952.2025.10958934
Citations
1
Primary Topic
Multilevel Inverters and Converters
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article
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article

Design and Analysis of a Boost Type Nine-Level Inverter with Reduced Switch and Capacitor Voltage Stress

N Gopinath, M. Kannan, Harsha Gobinath, R Saivarshini et al.
1 citations
Multilevel Inverters and Converters
0.73
article

Design and Analysis of a Boost Type Nine-Level Inverter with Reduced Switch and Capacitor Voltage Stress

N Gopinath, M. Kannan, Harsha Gobinath, R Saivarshini, Prakash Shunmugam
article en
1 citations

Abstract

This article proposes a boost type (BT) nine-level (9L) switched capacitor (SC) based transformerless inverter topology fo grid connected solar photovoltaic systems. It uses a single source, 10 switches, 2 diodes and 3 SCs. The voltage across the Sc is even which is only half of the output voltage v<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</inf>/2 and does not employ any complex algorithms for their voltage balancing. Power switches voltage stress is significantly low for the proposed topology and hence low total standing voltage per unit (TSV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p.u.</inf>). The different modes of operation and design of SC are presented. The simulation verification and prototype results are presented to confirm the operability of the proposed topology. Further, a detailed comparison of same art of topologies has been presented to highlight the features of the proposed topology.

Aarupadai Veedu Medical College & Hospital (IN), St. Joseph's Institute of Technology (IN), Saveetha University (IN)
Affordable and clean energy
Openalex Percentile: Top 29%
Multilevel Inverters and Converters
0.73
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Design and Analysis of a Boost Type Nine-Level Inverter with Reduced Switch and Capacitor Voltage Stress — N Gopinath, M. Kannan, et al. · (2025) | TGRS Research Map | TGRS