Performance Analysis of a New Single and Partial Double Error Correcting (SPDEC) Code with Soft Decision Decoding

Error Correcting Codes (ECCs) are employed for detection and correction of errors which are introduced by the channel noise or interference in modern communication system. In ECC, redundant bits are added in encoding process and these extra bits are utilized by the decoder for error detection and correction. The ECC is an integral part of most of the modern wired and wireless communication systems to make these systems reliable. In this paper, a new Single and Partial Double Error Correcting (SPDEC) code has been proposed for application in digital communication systems. The proposed <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$H$</tex> -matrix for PDEC code has been constructed with two different word lengths of 4-bit and 8-bit. Also performance of proposed SPDEC code has been analyzed by employing Soft Decision Decoding (SSD) method. It has been observed that the proposed SPDEC codes have better error performance and coding gains compared to related coding schemes.